1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a planar channel-type transistor in which n-type polysilicon and p-type polysilicon are used as the respective gate electrodes of n- and p-channel transistors.
2. Description of the Related Art
A planar channel-type transistor is the conduction type in which n- and p-channel transistors have mutually different gate electrodes; the common problem with the transistors of this type is that the boundary of these two gate electrodes cannot take an ohmic contact and that to reduce its resistance, either an upper layer of the individual gate electrode or an active region on a semiconductor substrate has to be combined with a high-melting-point metal in self-alignment to form metal silicide.
Attempts have been made to realize such an ohmic contact. For example, in a first conventional CMOS (complementary metal oxide semiconductor) transistor technology disclosed in Japanese Patent Laid-Open Publication No. Sho59-213156, as shown in FIGS. 2(a) and 2(b) of the accompanying drawings of the present specification, a gate electrode 21 of an n-channel region B on a first field insulation (SiO.sub.2) layer 20 has a three-layer structure composed of n.sup.+ polysilicon 23, n.sup.+ metal (molybdenum, Mo) silicide 25 and a high-melting-point metal (Mo) 27, while a gate electrode 22 of a p-type region A has likewise a three-layer structure composed of p.sup.+ polysilicon 24, p.sup.+ metal (Mo) silicide 26 and the above-mentioned high-melting-point metal (Mo) 27. At the boundary of the p- and n-channel regions, though the n.sup.+ polysilicon 23 and p.sup.+ polysilicon 24 assume a pn junction, the n.sup.+ metal silicide 25 and p.sup.+ metal silicide 26 are joined by an ohmic contact because of the high-melting-point metal (Mo) 27. Reference number 29 designates aluminum wiring insulated by a second field insulation (SiO.sub.2) layer 28.
FIGS. 3(a) to 3(c) of the accompanying drawings show a second conventional CMOS transistor technology disclosed in Japanese Laid-Open Publication No. Hei3-203366. FIG. 3(a) is a fragmentary schematic plan view of the conventional CMOS transistor in which p- and n-channel MOS transistors, FIG. 3(b) is an enlarged schematic cross-sectional view taken along line A-A' of FIG. 3(a), and FIG. 3(c) is an enlarged schematic cross-sectional view taken along line B-B' of FIG. 3(a). In this second conventional technology, as shown in FIG. 3(a), an n-well 32 is formed in a predetermined region of a p-type semiconductor substrate to define a p-channel transistor region 31 in which element forming regions are located as a p-type active region and a p-type gate electrode 34. A p-type substrate region adjacent to the p-channel transistor region 31 defines an n-channel transistor region 33 in which element forming regions are located as an n-type active region and an n-type gate electrode 35. Titanium silicide (indicated by diagonal lines in FIG. 3(a)) is formed in self-alignment alignment as an upper layer of each of the p- and n-type active regions and p- and n-type gate electrodes 34, 35, thus constituting gate electrodes. To a boundary (shared gate input contact 37) of the p- and n-type gate electrodes 34, 35, the input aluminum wiring 36 is connected via which a gate input signal is to be transmitted. With the shared gate input contact 37 as their boundary, the silicide at the upper layer of the first gate electrode 34 and that at the upper layer of the second gate electrode 35 are separated from each other. Namely, after a shared gate electrode is formed of the same polysilicon layer 38, the polysilicon layer 38 except an intermediate region between the p- and n-channel MOS transistors 31, 33 is combined with titanium (Ti) to form silicide. And at the shared gate input contact 37, the input aluminum wiring 36 is connected to the silicide of each of the first and second gate electrodes 34, 35 as well as to the polysilicon layer 38 beneath the intermediate region between the first and second electrodes 34, 35.
Further, on opposite sides of each gate electrode 34, 35, source and drain regions for each of the p- and n-channel MOS transistors 31, 33 are provided. The source region of the p-channel MOS transistor 31 is connected to the supply potential (Vcc) aluminum wiring 39, and the source region of the n-channel MOS transistor 33 is connected to the ground potential (GND) aluminum wiring 40. And the drain regions of the p- and n-channel MOS transistors 31, 33 are connected to output aluminum wiring 41 via the corresponding contact holes 37.
More specifically, as shown in FIG. 3(b), on the p-type semiconductor substrate 43 over the entire surface except the active region, a field oxide film 44 is formed, and over the entire surface, a gate oxide film 45 is formed, whereupon the nondoped polysilicon is patterned into a gate polysilicon electrode 46 using lithography and etching technique.
Then phosphorus (P) is doped in the n-channel MOS transistor region to form an oxide film over its entire surface.
Subsequently, as shown in FIG. 3(c), photoresist is coated over a part (the exposed portion of the polysilicon layer 38 in FIG. 3(a)) of the joint of gates of p- and n-channel MOS transistors 31, 33 using lithography, and then the entire surface of the photoresist is etched to form opposite sidewall oxide films 47 at the gates of the transistor.
Then titanium (Ti) is sputtered over the entire surface and heated to form titanium silicide 48 as the diffused layer and polysilicon react with titanium (Ti). At that time, since the oxide film does not react with titanium (Ti), the gate polysilicon layer between p- and n-channel MOS transistors 31, 33 does not become silicide. Arsenic (As) is introduced into the n-channel MOS transistor region, and boron (B) is introduced into the p-channel MOS transistor region to dope the gate, source and drain of the n-channel transistor as N.sup.+ and those of the p-channel transistor as P.sup.+.
After that, an interlayer insulation film 49 grows and contact holes; 42 are formed, and then aluminum wiring 50 is patterned.
Thus in an effort to prevent mutual impurity diffusion through the individual silicide layers 48 on gate electrodes 34, 35, the respective silicide layers 48 on p- and n-type gates are mutually isolated at the gate junction and are then interconnected when the shared gate input contact 37 is formed.
However, these conventional technologies have been encountered with the following problems. For example, in the first conventional technology, although an ohmic contact between different conduction-type gate electrodes can be achieved, part of the high-melting-point metal would stay on the gate electrodes as residue so that either the upper layer of each gate electrode or the active region can be combined with the high-melting-point metal to form the silicide but only out of self-alignment.
In the second conventional technology, although mutual impurity diffusion between the p- and n-type gate electrodes through the silicide layers can be prevented, either downsizing of the individual elements or reducing the total number of necessary process steps is difficult to realize. If a silicide layer was formed merely in self-alignment on either the individual gate electrode or the active region, a pn junction would have been formed near the boundary of the p- and n-type gate electrodes so that chiefly only the thin silicide layer of each gate electrode would have become conductive, thus resulting in a non-stable semiconductor device.